High-speed serial transceivers are commonly used in high-performance field programmable gate array (FPGA) devices. Examples include the Xilinx Virtex II Pro device family, described in Xilinx, Inc., “Virtex-II Pro Platform FPGA Handbook,” August 2004, UG012 (v3.0), and the Altera Stratix GX device family, described in Altera Corporation, “Stratix GX FPGA Family Datasheet,” December 2004, DS-STXGX-2.2. Such devices are capable of driving optical components and backplane interfaces at high speeds without any external circuitry other than a small set of passive components for termination and bias. The apparent advantage is the ability to implement a communication system in which everything from the backplane to the optics is reconfigurable.
Typical speeds on the serial line range from several hundred megabits per second to a few gigabits per second. For example, the operating range of the Rocket I/O block in a Xilinx Virtex II Pro device is between 622 Mb/s and 3.125 Gb/s. The choice of the operating range is typically a market driven tradeoff between the number of applications that a device can cover and the complexity and cost of the embedded transceiver.
Many data networking and telecom applications require that the serial line operate at multiple speeds, some of which are outside the transceiver's nominal range. For example, a gigabit Ethernet device is often implemented as a dual-speed system that can run at either the nominal 1 Gb/s speed or the reduced 100 Mb/s speed. See, for example, IEEE Standard 802.3, “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications,” March 2002. Furthermore, reconfigurable communication systems generally require a high degree of flexibility, with a wide range of communication speeds being an important dimension. When the system is in high-speed mode, the signaling rate on the interface is high enough to warrant the use of high-speed serial transceivers. However, the signaling rate in the low-speed mode is more appropriate for a general-purpose I/O block, typically using a different set of pins than those used for the high-speed serial transceiver.
Although it is possible to implement an external circuit that routes the signal to different pins depending on the mode the system is in, such a design would result in reduced system density, which is an undesirable property in many cases. On the other hand, combining a general-purpose I/O block with the high-speed serial transceiver using the same set of pins would likely result in various technical and economic challenges that would discourage the device vendor from implementing it. Finally, a brute-force approach of simply extending the operating range of the transceiver is not practical, because of the finite frequency range in which the phase locked loop (PLL) circuit in the clock and data recovery (CDR) block of the receiver can operate. A wider range requires a more complex and more expensive CDR block in the receiver. Economic factors thus limit the practical range of frequencies for which the clock and data can be recovered.
Accordingly, a need exists for an improved approach to accommodating a range of communication speeds, including one or more sub-nominal speeds, in a communication device having a serial transceiver or other type of receiver.